(1) Field of the Invention
The present invention relates to a decoder circuit, more particularly to a decoder circuit preferably applied to a memory address decoder circuit fabricated in the form of a complementary metal oxide semiconductor (C-MOS).
(2) Description of the Prior Art
As is well known, decoder circuits generally function to decode one digital signal and to transform it into another digital signal. In a semiconductor memory, decoder circuits decode memory addresses for selecting a desired word line and bit line to obtain access to the specific memory cell at the cross point therebetween. That is, in a semiconductor memory, decoder circuits are used as word decoder circuits and column decoder (bit decoder) circuits.
In recent years, various new types of semiconductor memories have been proposed. Along with the advances made in semiconductor memories, various new types of word decoder and column decoder circuits having smaller size, higher density packaging, or higher operation speeds have been proposed.
Up until now, however, it has not been possible to achieve all three of these features in a decoder circuit simultaneously.